1. Field of the Invention
The present invention relates to a technology to adjust an offset voltage generated in a differential amplifier circuit.
2. Description of Related Art
In such a differential amplifier circuit, an offset voltage is generated in consequence of an inherent product characteristic of the transistors that constitute the differential pair. In most cases, an offset adjustment circuit is provided to cancel the offset voltage.
FIG. 5 shows an offset adjustment circuit, which includes multiple offset adjustment transistors 105a, 105b, 106a, 106b, and switches 107a, 107b, 108a, 108b connected in parallel with the transistors 102, 103 that constitute the active load on a differential amplifier circuit 101. This structure cancels out the offset voltage by switching the ON and OFF states of the switches 107a, 107b, 108a, 108b according to the offset voltage and selecting the transistors 105a, 105b, 106a, and 106b. 
Japanese Patent Application Laid Open No. Hei 8(1996)-213855 shows an offset adjustment circuit including weighted transistors.